This disclosure relates to power networks of integrated circuits. Typically, a power network of an integrated circuit (IC) chip includes a plurality of layers of conductive lines which are arranged, for example, as a mesh network, and a plurality of interlayer vias that interconnect different layers of conductive lines. In the mesh network, conductive lines in an upper layer of the IC cross over conductive lines in a lower layer. Corresponding to where the conductive lines in the upper layer overlap with the conductive lines in the lower layer, interlayer vias and conductive segments in intermediate conductive layers are disposed to conductively couple the conductive lines in the upper layer with the conductive lines in the lower layer.
Power gating is a technique used in IC design to reduce power consumption by shutting off the current to blocks of the circuit that are not currently in use. In addition to reducing stand-by or leakage power, power gating has the benefit of enabling CMOS IC testing for the presence of manufacturing faults.